1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to clock generation circuits for radiation hardened integrated circuits.
2. Related Art
Increasingly, space-based communication systems are including integrated circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they are high speed and low power. The CMOS ICs use little power compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These circuit disturbances are known as single event effects (SEE) and, as single event upsets (SEU) when corrupting data in storage elements. Radiation hardened latches are well known and are used, effectively, to reduce or to eliminate SEU in space-based IC registers, latches and other storage elements. These radiation hardened storage elements are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
However, over time, as circuit performance has increased, the propagation delay through the logic between the radiation hardened latches or registers has been reduced to within an order of magnitude of the duration of an SEE. For example, a pipelined logic chip operating at 200 MHz can have 3-3.5 nanoseconds allocated for logic propagation delays between registers. A single event upset occurring in the logic can cause an invalid result for 0.5-1.0 nanoseconds because this is a significant amount of time with respect to a pulse width. Such an event occurring in a clock distribution chain causes a more widespread and potentially a much more serious result.
Typically, chip clocks are received by a receiver connected to a bonding pad of the IC. The receiver buffers and redrives the clock, typically, to multiple locations on the chip. At each of these locations, the clock is again buffered and redriven. This rebuffered clock can further distributed to multiple locations, where it can again be rebuffered and redriven. The clock distribution can be represented as a tree spreading out from the original receiver.
The effects from an event occurring in a clock tree can cause a transient in the clock signal on part of the clock tree of approximately 0.5 nanoseconds, which can appear as a false clock pulse. Further, the number of latches and registers affected by the false clock pulse is random and depends on where in the tree the event occurs. Such a false clock pulse can clock registers causing the registers to latch invalid data. The invalid latched data can be passed from the initial registers through the next logic stage. This can result in multiple uncorrectable multi-bit logic errors.
The severity of this problem only increases with greater levels of very large scale integration (VLSI) circuit integration because these higher levels of integration achieve higher performance through smaller features. For example, with circuits operating in the 1 GHz clock range, a single event could wipe out an entire clock cycle for the affected part of the IC logic. Thus, it can be seen that clock tree SEE immunity is critical to preventing logic errors.
For example, FIG. 1 illustrates a typical state of the art scan d-flip-flop (scan dff) 100. The scan d flip-flop 100 includes a 2:1 multiplexer 102, which is coupled to a first level sensitive latch 104. The first level sensitive latch 104 is coupled to a second level sensitive latch 106. The scan dff 100 is clocked by a clock signal 107. The clock signal 107 is split into complementary signals by inverting clock signal 107 with inverter 108. The complementary clock signals are provided to first level sensitive latch 104 and second level sensitive latch 106, gating first and second pairs of pass gates 110, 112 and 114, 116, respectively.
When selected, an input DATAIN 118 passes through the 2:1 multiplexer 102 to the first pair of pass gates 110, 112 as complementary outputs 120, 122 of multiplexer 102. When the clock signal 107 is low, pass gates 110, 112, are turned on so that data and complementary outputs 120, 122 are passed to first level sensitive latch 104 and, tentatively, are stored therein. With the clock signal 107 low, the second pair of pass gates 114, 116 are contemporaneously turned off, and isolate the second level sensitive latch 106 from outputs 124, 126 of the first level sensitive latch 104.
The rising edge of clock signal 107 turns on the second pair of pass gates 114, 116 as the output of inverter 108 falls, simultaneously, to turn off the first pair of pass gates 110, 112. When the first pair of pass gates 110, 112 are turned off, the complementary outputs 120, 122 are isolated from the first level sensitive latch 104 and, so, data is latched in the first level sensitive latch 104. When the second pair of pass gates 114, 116 are turned on, outputs 124, 126 of the first level sensitive latch 104 are passed to the second level sensitive latch 106. The state of outputs 124, 126, is stored, tentatively, in the second level sensitive latch 106 and, simultaneously, is passed out on an output DATAOUT 128. When clock signal 107 falls, on the next clock cycle, the second pair of pass gates 114, 116 are turned off, isolating the second level sensitive latch 106 from the outputs 104, 126 of first level sensitive latch 104, latching data in the second level sensitive latch 106 to complete the clock cycle.
Normally, when the clock signal 107 is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN 118 meet a setup (i.e., be valid for a specified period prior to the rise of clock signal 107) and hold (i.e., remain valid for a specified period after the rise of clock signal 107) timing requirements. At any time, other than this window around clock signal 107 rising, the state of input DATAIN 118 is specified as a xe2x80x9cdon""t carexe2x80x9d condition.
Unfortunately, an upsetting event occurring in the clock tree prior to clock signal 107 can cause a false clock pulse on clock signal 107. Since input DATAIN 118 is specified as a xe2x80x9cdon""t care,xe2x80x9d a falling edge of a false clock pulse on clock signal 107 could cause the first level sensitive latch 104 to switch states, inadvertently storing data. Further, when the input clock returns high, that invalid level can be passed to the second level sensitive latch 106 and out of the scan dff 100 on output DATAOUT 128. The false clock pulse is a pulse perturbated by an SEE.
Thus, for reasons stated above, and for other reasons stated below, which will become apparent to those skilled in the relevant art upon reading and understanding the present specification, what is needed are clock generation circuits with reduced SEE sensitivity.
The above mentioned problems with clock generation circuits and radiation hardened storage elements and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
Briefly, the present invention is a clock splitter circuit for providing a Single Event Upset (SEU) tolerant clock for clocking latches in a space-based environment. The splitter circuit can include an event offset delay circuit. The event offset delay circuit can receive an undelayed clock signal and generate an inverted undelayed clock signal, a delayed clock signal and an inverted delayed clock signal. The delayed clock signal and inverted delayed clock signal are delayed by a known duration of Single Event Effects (SEE) on logic. The delayed and undelayed clock signals can be passed to a pair of event blocking filters. SEE induced signal perturbations that may be present in the delayed, undelayed, inverted and uninverted clock signals can be blocked by the pair of event blocking filters. Each event blocking filter generates a pair of in-phase inverted clock output signals. An output of each of the event blocking filters is cross-coupled to an input of the other, such that the pairs of in-phase inverted clock output signals are not low simultaneously. Each pair of in-phase inverted clock output signals drives one of a pair of inverting clock drivers. Thus, the pair of inverting clock drivers provide a complementary pair of SEU tolerant non-overlapping clock output signals to one or more latches from a single undelayed input clock signal.
In an embodiment of the present invention, a clock splitter circuit includes an event offset delay circuit, and a first event blocking filter and a second event blocking filter coupled to the event offset delay circuit.
In one embodiment of the present invention, the circuit can further include a first clock driver and a second clock driver coupled to the first event blocking filter and the second event blocking filter.
In one embodiment of the present invention, the event offset delay circuit includes first, second, third, fourth and fifth inverters coupled in series, where an input to the first inverter is an undelayed clock signal and an output of the first inverter is an inverted undelayed clock signal, where an output of the fourth inverter is a delayed clock signal, where an output of the fifth inverter is an inverted delayed clock signal, where the undelayed clock signal and the delayed clock signal are coupled to the first event blocking filter, and where the inverted undelayed clock signal and the inverted delayed clock signal are coupled to the second event blocking filter.
In one embodiment of the present invention, each of the first and the second event blocking filters includes three series coupled PFETs, a PFET coupled in parallel with two of the three series connected PFETs, and four series coupled NFETs, a drain-source region of one of the four series coupled NFETs being coupled at a first of two in-phase outputs of the event blocking filter to a drain-source region of a third PFET of the three series coupled PFETs, a source-drain region of the third PFET being coupled to a second of the two in-phase outputs.
In one embodiment of the present invention, the first PFET of the three series coupled PFETs is gated by the delayed clock signal and the second PFET of the three series coupled PFETs is gated by undelayed clock signal.
In one embodiment of the present invention, a gate of the third PFET is coupled to ground.
In one embodiment of the present invention, a gate of the parallel connected PFET is driven high to enable the event blocking filter.
In one embodiment of the present invention, each of the first and second clock drivers is an inverting clock driver and where each of the clock drivers includes a PFET, a source-drain region of the PFET coupled to a supply voltage, a gate of the PFET gated by the first of the in-phase outputs of the event blocking filter, and an NFET, a source-drain region of the NFET coupled to ground, a gate of the NFET gated by the second of the in-phase outputs, a drain-source region of the PFET coupled to a drain-source region of the NFET and coupled to an output of the clock driver.
In one embodiment of the present invention, a clock splitter circuit for providing an SEU tolerant clock to latches in a space-based environment is disclosed, where the clock splitter circuit includes an event offset delay circuit receiving an undelayed clock signal and generating a delayed clock signal and the undelayed clock signal, a first event blocking filter receiving and combining the undelayed clock signal and the delayed clock signal to provide a first and a second of two in-phase outputs, and a first clock driver being driven by the first and the second in-phase outputs to provide a clock driver output signal.
In one embodiment of the present invention, the circuit further includes a second event blocking filter receiving an undelayed inverted clock signal and a delayed inverted clock signal from the event offset delay circuit, and a second clock driver being driven by the second event blocking filter.
In one embodiment of the present invention, the event offset delay circuit generates the undelayed inverted clock signal and a delayed inverted clock signal, the undelayed clock signal and the delayed clock signal being provided to one of the first and the second in-phase outputs and the undelayed inverted clock signal and the delayed inverted clock signal being provided to the other of the first and the second in-phase outputs.
In one embodiment of the present invention, a low signal at one of the first and the second in-phase outputs of the first and the second event blocking filters prevents the other of the first and the second in-phase outputs from being pulled low.
In one embodiment of the present invention, the event offset delay circuit is a series of coupled inverters.
In one embodiment of the present invention, the event offset delay circuit is 5 series coupled inverters, the undelayed inverted clock signal being an output of a first of the 5 series coupled inverters, the delayed clock signal being an output of a fourth of the 5 series coupled inverters and the delayed inverted clock signal being an output of a fifth of the 5 series coupled inverters.
In one embodiment of the present invention, each of the first and the second event blocking filters includes three series coupled devices of a first conduction type, four series coupled devices of a second conduction type, a conduction terminal of one of the three series coupled devices being coupled to a conduction terminal of the four series coupled devices, and a device of the first conduction type being coupled in parallel with two of the three series coupled devices.
In one embodiment of the present invention, one of the first and the second in-phase outputs is at a coupling point of the parallel coupled device and the other of the pair of in-phase outputs is at the coupled of the three series coupled devices with the four series coupled devices.
In one embodiment of the present invention, the devices of the first conduction type are P-type field effect transistors (FETs) and the devices of the second conduction type are N-type FETs, the first and the second in-phase outputs being separated by one of the three series coupled PFETs with its gate coupled to ground.
In one embodiment of the present invention, a clock splitter circuit for providing an SEU tolerant clock to latches in a space-based environment is disclosed, where the clock splitter circuit includes an event offset delay means for generating an undelayed inverted clock signal, a delayed clock signal and a delayed inverted clock signal responsive to an undelayed clock signal, the delayed clock signal being delayed from the undelayed clock signal and the inverted delayed clock being delayed from the undelayed inverted clock signal by a period of at least equal to a single event effect duration, and a pair of event blocking filters means for blocking single event effects in the undelayed clock signal, the undelayed inverted clock signal, the delayed clock signal or the delayed inverted clock signal and generating a pair of in-phase clock output signals therefrom.
In one embodiment of the present invention, the circuit further includes a pair of clock driver means for providing a pair of non-overlapping clock signals responsive to a corresponding pair of in-phase clock output signals from the event blocking filters means.
In one embodiment of the present invention, each of the pair of event blocking filter means includes enable means for enabling the event blocking filter, feedback means for preventing the in-phase outputs from the event blocking filter from switching, resistive means for resistively isolating the pair of in-phase outputs from the event blocking filter means, and means for comparing the delayed clock signal with the undelayed clock signal, the pair of in-phase clock output signals being generated responsive to the delayed and undelayed clock signals.
In one embodiment of the present invention, an integrated circuit (IC) chip for space-based operation is disclosed, including an SEU tolerant clock splitter, the clock splitter includes an event offset delay generating an undelayed inverted clock signal, a delayed clock signal and a delayed inverted clock signal responsive to an undelayed clock signal, the delayed clock signal being delayed from the undelayed clock signal and the the inverted delayed clock being delayed from the undelayed inverted clock signal by a period of at least equal to a single event effect duration, and a pair of event blocking filters each generating a coupled pair of in-phase clock output signals, a first of the pair of event blocking filters receiving the undelayed clock signal and the delayed clock signal, generating a pair of inverted in-phase clock output signals and blocking single event effects from passing to the pair of generated inverted in-phase clock output signals, a second of the pair of event blocking filters receiving the undelayed inverted clock signal and the delayed inverted clock signal, generating a pair of uninverted in-phase clock output signals and blocking single event effects from passing to the pair of generated uninverted in-phase clock output signals, where the clock output in-phase signals from one of the pair of event blocking filters are low preventing the in-phase clock output signals from an other of the pair of event blocking filters from being driven low.
In one embodiment of the present invention, the integrated circuit chip further includes a pair of inverting clock drivers, the in-phase clock output signals from each of the pair of event blocking filters being coupled to a corresponding one of the pair of inverting clock drivers, each of the pair of inverting clock drivers providing a pair of non-overlapping clock output signals.
In one embodiment of the present invention, each of the pair of event blocking filters includes a pair of series coupled PFETs, the pair being gated by the delayed and the undelayed clock signals, a PFET coupled in parallel with the pair of series coupled PFETs between a supply voltage and a first of the pair of in-phase clock output signals, the parallel coupled PFET being gated by an enable signal, a grounded gate PFET, a source-drain region of the grounded gate PFET being coupled to the first of the pair of in-phase clock output signals, the drain-source region of the grounded gate PFET being coupled to a second of the pair of in-phase clock output signals, and four series coupled NFETs coupled between the second of the in-phase clock output signals and ground, a gate of one of the NFETs being coupled to the second of the pair of in-phase outputs of the other of the pair of the event blocking filters.
In one embodiment of the present invention, each of the clock drivers includes a PFET, a source-drain region of the PFET coupled to a supply voltage, a gate of the PFET gated by the first of the pair of in-phase clock output signals, and an NFET, a source-drain region of the NFET coupled to ground, a gate of the NFET gated by the second of the pair of in-phase clock output signals, a drain-resource region of the PFET coupled to a drain-source region of the NFET and coupled to a clock driver output.
In one embodiment of the present invention, a method of clocking an integrated circuit chip is disclosed including generating an undelayed complementary pair of clock signals, generating a delayed complementary pair of clock signals, generating a first in-phase clock signal pair from an uninverted undelayed clock signal of the undelayed complementary pair of clock signals and an uninverted delayed clock signal of the delayed complementary pair of clock signals, and generating a second in-phase clock signal pair from an inverted undelayed clock signal of the undelayed complementary pair of clock signals and an inverted delayed clock signals of the delayed complementary pair of clock signals.
In one embodiment of the present invention, the method further includes generating a first latch clock signal from the first in-phase clock signal pair, and generating a second latch clock signal from the first in-phase clock signal pair, the first and the second latch clock signals clocking the integrated circuit.
In one embodiment of the present invention, the first and second latch clocks are non-overlapping clocks.
In one embodiment of the present invention, both the first and the second in-phase clock signal pairs must be high before either can be pulled low.
In one embodiment of the present invention, the step of generating the delayed complementary pair of clock signals further includes enabling clock generation.
In one embodiment of the present invention, a clock splitter circuit is disclosed including an event offset delay circuit and first and second event blocking filters coupled to the event offset delay circuit and generating a pair of undelayed complementary clocks signals, where an upset occurring in an input clock tree prior to the first and the second event blocking filters is not propagated to the pair of undelayed complementary clock signals.
In one embodiment of the present invention, the event offset delay circuit includes first, second, third, fourth and fifth inverters coupled in series, where an input to the first inverter is an undelayed clock signal and an output of the first inverter is an inverted undelayed clock signal, where an output of the fourth inverter is delayed from undelayed clock signal by a delay approximately equal to a duration of an upset, where an output of the fifth inverter is an inverted delayed clock signal delayed from the inverted undelayed clock signal by a delay approximately equal to the duration of an upset, where the undelayed clock signal and the delayed clock signal are coupled to the first event blocking filter, and where the inverted undelayed clock signal and the inverted delayed clock signal are coupled to the second event blocking filter.
It is an advantage of the invention that integrated circuit chip SEE sensitivity can be reduced.
It is another advantage of the invention that integrated circuit power can be reduced.
It is yet another advantage of the invention that integrated circuit chip clock tree SEE sensitivity can be reduced.
It is yet another advantage of the invention that timing related SEU sensitivity is reduced on space-based integrated circuit chips.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digits in the corresponding reference number.